(1) Field of the Invention
This invention relates to complementary MOS integrated circuits (hereinafter referred to as "CMOS circuits", when applicable), and more particularly to a CMOS circuit in which the generation of noises can be suppressed even when the drive capacity of an output circuit is increased, for instance, for high speed operation.
(2) Description of the Prior Art
FIG. 1 shows a conventional CMOS output circuit. In FIG. 1, reference numeral 1 designates an input terminal; 2, an output terminal; 3, a power source terminal to which a voltage Vcc is applied as a power source; 4, a ground (GND) terminal; 5, a P-channel MOS transistor; and 6, an N-channel MOS transistor.
In FIG. 1, when an input voltage applied to the input terminal 1 is at the ground (GND) potential, the P-channel MOS transistor 5 is turned on, while the N-channel MOS transistor 6 is turned off, so that the output terminal 2 is held at the potential Vcc. When, in contrast, the input voltage is at Vcc, the P-channel MOS transistor 5 is turned off, while the N-channel MOS transistor 6 is turned on, so that the output terminal 2 is held at the ground (GND) potential. When the voltage is between the GND and Vcc, the potential of the output terminal 2 is determined according to the so-called "on-resistance ratio" of the MOS transistors 5 and 6.
FIG. 2 is a graphical representation indicating a penetration current (Icc) with the input voltage in FIG. 1. In FIG. 2, reference character V.sub.THN designates the threshold voltage of the N-channel MOS transistor and V.sub.THP, the threshold voltage of the P-channel MOS transistor. As is apparent from FIG. 2, in general, the P-channel MOS transistor 5 and the N-channel MOS transistor 6 are so selected that the penetration current (I.sub.cc) reaches the peak value when the input potential is about 1/2 Vcc.
FIG. 3 is a circuit diagram showing a drive circuit for driving the CMOS output circuit of FIG. 1 (hereinafter referred to as "pre-output circuit", when applicable). The pre-output circuit is made up of a P-channel MOS transistor 7 and an N-channel MOS transistor 8, to drive the CMOS output circuit of FIG. 1.
FIG. 6 shows the CMOS output circuit installed on a printed circuit board. As shown in FIG. 6, inductance components 200 and 201 formed by the frame and conductors of the integrated circuit and the wiring of a printed circuit board are connected between the power source terminal 3 and an external power source Vcc' and between the ground (GND) terminal 4 and the ground terminal GND' of the external power source, respectively.
Next, a conventional three-state complementary MOS integrated circuit is as shown in FIG. 8.
In FIG. 8, reference numeral 11 designates an input terminal; 12, an output terminal; 13, a power source terminal (a first power source).to which a voltage Vcc is supplied; 14, a ground terminal (a second power source); 15, a control input terminal to which a first control signal .phi. is applied; 16, a control input terminal to which a second control signal .phi. is supplied; P1, P2, P3 and P4, p-channel MOS transistors; 18, a first analog switch consisting of the transistors N4 and P4; 19, a first parallel transistor circuit consisting of the transistors P2 and P3; 20, a second parallel transistor circuit consisting of the transistors N2 and N3; 21, a pre-output circuit consisting of the first analog switch 18 and the first and second parallel transistor circuits 19 and 20; and 22, an output circuit including the transistors P1 and N1.
The conventional three-state complementary MOS integrated circuit thus organized operates as follows.
When the control input terminal 15 is held at a low level (hereinafter referred to merely as "L", when applicable) and the control input terminal 16 is held at a high level (hereinafter referred to merely as "H", when applicable), the transistors P3 and N3 are rendered non-conductive (off) whereas the transistors P4 and N4 are rendered conductive (on). Therefore, if the input terminal 11 is at "L", then an "L" signal is provided at the output terminal 12; and if the input terminal 11 is at "H", then an "H" signal is provided at the output terminal 12. On the other hand, when the control input terminal 15 is held at "H" and the control input terminal 16 is at "L", the transistors P3 and N3 are rendered conductive (on). Therefore, irrespective of the level at the input terminal 11, the transistors Pl and Nl are turned off, and the output terminal 12 is held high in impedance.
The output circuit which is obtained by rendering the transistors P4 and N4 of FIG. 8 conductive (on) and disregarding the "on-resistances" of these transistors P4 and N4, is equivalent to that of an ordinary complementary MOS circuit as shown in FIG. 1.
In order to meet the recent requirement of high speed operation, the current capacity (or drive capacity) of the MOS transistors forming the output circuit has been set to a large value, for instance 200 to 300 mA with Vcc= 5V. Accordingly, the above-described penetration current is also increased, and a spike voltage e=-(di/dt)) induced by the inductance components 200(L.sub.1) and 201(L.sub.2) in FIG. 6 is increased, thus resulting in an erroneous operation. FIG. 7 shows one example of a waveform at the output terminal 2, which includes a spike noise. In FIG. 7, the horizontal axis represents time whereas the vertical axis represents voltage. As is apparent from FIG. 7, when the output signal changes from "L" to "H" or vice versa, a large spike noise is generated, thus causing an erroneous operation of a circuit which is driven by the output of the output circuit.